1. Field
The embodiments described herein relate to a non-volatile semiconductor memory device that is able to electrically rewrite data, and a semiconductor device.
2. Description of the Related Art
Conventional LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the storage capacity of a memory has been generally increased by reducing (miniaturizing) the dimension of each device, in recent years, the miniaturization has become difficult in terms of cost and technology. Although the miniaturization requires the improved photolithography technology, the cost of the lithography process has been increasingly increased. Even if the miniaturization is achieved, it is expected that a physical limitation such as the breakdown voltage between devices will be reached, unless the drive voltage or the like is scaled. In other words, it will probably be difficult for a memory to operate as a device.
In recent years, therefore, for a more integrated memory, a number of semiconductor memory devices including three-dimensionally arranged memory cells have been proposed.
One conventional semiconductor memory device including three-dimensionally arranged memory cells is a semiconductor memory device including a cylindrical structure transistor. The semiconductor memory device including a cylindrical structure transistor includes multilayered polysilicon as the gate electrode and a columnar semiconductor. The columnar semiconductor functions as the channel (body) of the transistor. Around the columnar semiconductor, a plurality of charge accumulation layers are provided via tunnel insulating layers, the charge accumulation layers being for accumulating charges. Further, the charge accumulation layers have a block insulating layer formed therearound. The configuration including these polysilicon, columnar semiconductor, tunnel insulating layer, charge accumulation layer, and block insulating layer is called a memory string.
In the erase operation of a conventional semiconductor memory device including the three-dimensionally arranged memory cells, in the selected block, the voltage of the columnar semiconductor as the memory cell body is boosted using the GIDL current (Gate Induced Drain Leakage Current), and the voltage of the word-line is kept at, for example, 0V, thereby performing the data erase. At the same time, in the unselected block, the voltage of the word-line is kept in the floating state, and if the potential of the columnar semiconductor is increased by the GIDL current, the potential of the floating word-line is increased to a predetermined potential due to capacitive coupling. This prevents data erase in the unselected block. This scheme requires, without supplying a special voltage to the word-line in the unselected block, only cutting off the driving transistor in the row decoder, thereby providing the efficient erase operation.
This scheme has a problem, however, that even if the voltage of the word-line in the unselected block is increased due to capacitive coupling, a subsequent leak current of the driving transistor can cause the voltage of the word-line in the unselected block to be gradually decreased. The voltage of the word-line in the unselected block being decreased below a predetermined voltage due to the leak current can cause a data erasing error in the unselected block. Accordingly, there is a need for a laminated non-volatile semiconductor memory device that may efficiently perform the erase operation and prevent the erasing error.